The present invention relates to an output buffer circuit, and, more particularly, to an output buffer circuit that outputs an output signal having gentle rising and falling edges and a slew-rate control type output buffer circuit.
For example, an interface, such as USB (Universal Serial Bus), which is used to connect a computer to a keyboard and achieves slow data transfer, is equipped with an output buffer circuit which has long signal rising and falling times. The use of a signal which has long rising and falling times makes it unnecessary to provide a bus cable with a shield for preventing undesirable radiation.
FIG. 1 is a schematic circuit diagram of a first prior art output buffer circuit 11.
The output buffer circuit 11 has a drive circuit 12 and first and second control circuits 13 and 14. The drive circuit 12 has a P channel (PMOS) transistor TP1 and an N channel (NMOS) transistor TN1 which are connected in series between a high-potential power supply VDD and a low-potential power supply VSS. A node between the PMOS and NMOS transistors TP1 and TN1 is connected to an output terminal 15 of the output buffer circuit 11.
The first control circuit 13 has a PMOS transistor TP2 and two NMOS transistors TN2 and TN3, which are connected in series between the high-potential power supply VDD and low-potential power supply VSS. A node between the PMOS transistor TP2 and the adjacent NMOS transistor TN2 is connected to the gate of the PMOS transistor TP1. An external input signal VIN is applied to the gates of the individual transistors TP2, TN2 and TN3. In response to the external input signal VIN, the transistors TP2, TN2 and TN3 supply a control signal VP to the gate of the output transistor TP1.
The second control circuit 14 has two PMOS transistors TP3 and TP4 and an NMOS transistor TN4, which are connected in series between the high-potential power supply VDD and low-potential power supply VSS. A node between the PMOS transistor TP4 and the adjacent NMOS transistor TN4 is connected to the gate of the NMOS transistor TN1. The external input signal VIN is applied to the gates of the individual transistors TP3, TP4 and TN4. In response to the external input signal VIN, the transistors TP3, TP4 and TN4 supply the control signal VN to the gate of the output transistor TN1.
Each of the PMOS and NMOS transistors TP1 and TN1 has a relatively large transistor size (gate width). That is, each of the PMOS and NMOS transistors TP1 and TN1 has a low impedance with respect to the output terminal 15. The NMOS transistors TN2 and TN3 of the first control circuit 13 control the amount of current flowing into the low-potential power supply VSS, so that the control signal VP having a gentle falling edge is supplied to the PMOS transistor TP1. As a result, an external output signal VOUT which has a gentle rising edge is output from the output terminal 15. The PMOS transistors TP3 and TP4 of the second control circuit 14 control the amount of current flowing out of the high-potential power supply VDD, so that a control signal VN having a gentle rising edge is supplied to the NMOS transistor TN1. As a result, the external output signal VOUT which has a gentle falling edge is output from the output terminal 15.
In other words, the waveform of the output signal VOUT has gentle transition by controlling the waveform transition times of the control signals VP and VN that are respectively applied to the gates of the output transistors TP1 and TN1 by the first and second control circuits 13 and 14.
The minimum values and maximum values of the rising time and falling time of the output signal VOUT are specified by specifications. However, the waveforms of the control signals VP and VN are greatly affected by variations in the sizes of the individual transistors TP2–TP4 and TN2–TN4 or variations in the wiring capacitances between the first and second control circuits 13 and 14 and the output transistors TP1 and TN2, which are factors of the manufacturing process, a variation in supply voltage or a temperature change. That is, variations in the rising and falling times of the external output signal VOUT are increased, so that the rising and falling times exceed the specified ranges.
FIG. 2 is a schematic circuit diagram of a second prior art slew-rate control type output buffer circuit 211. The output buffer circuit 211 adjusts the inclination (slew rate) of the input waveform to the gate of an output driving transistor to reduce the consumed current at the time the output signal varies. The output buffer circuit 211 has output driving transistors (simply called “output transistors”) T1 and T2, slew-rate control circuits 212 and 213 which perform the ON/OFF control of the respective output transistors T1 and T2 in response to the external input signal VIN, and a delay circuit 214.
The first output transistor T1, which is a PMOS transistor, and the second output transistor T2, which is an NMOS transistor, are connected in series between a high-potential power supply VDD and low-potential power supply VSS, with a node between the transistors T1 and T2 being connected to an output terminal 215 of the output buffer circuit 211. Specifically, the first output transistor T1 has a source connected to the high-potential power supply VDD and a drain connected to an output terminal 215, with a control signal VP from the first control circuit 212 being applied to the gate of the transistor T1. The second output transistor T2 has a source connected to the low-potential power supply VSS and a drain connected to the output terminal 215, with a control signal VN from the second control circuit 213 being applied to the gate of the transistor T2.
The first control circuit 212 has a PMOS transistor T11 and NMOS transistors T12 and T13, connected in series between the high-potential power supply VDD and low-potential power supply VSS, and an NMOS transistor T14 connected in parallel to the NMOS transistor T13. The PMOS transistor T11 has a source connected to the high-potential power supply VDD and a drain connected to the drain of the NMOS transistor T12, with an external input signal VIN being applied to the gates of both transistors T11 and T12. The source of the NMOS transistor T12 is connected to the drain of the NMOS transistor T13 whose source is connected to the low-potential power supply VSS. The NMOS transistor T14 has a relatively large ON resistance and its gate is connected to the high-potential power supply VDD. Therefore, the NMOS transistor T14 is normally ON and serves as a resistor element.
The second control circuit 213 has PMOS transistors T21 and T22 and an NMOS transistor T23, connected in series between the high-potential power supply VDD and low-potential power supply VSS, and a PMOS transistor T24 connected in parallel to the PMOS transistor T21. The PMOS transistor T21 has a source connected to the high-potential power supply VDD and a drain connected to the source of the PMOS transistor T22, with the external input signal VIN being applied to the gates of both transistors T21 and T22. The drain of the PMOS transistor T22 is connected to the drain of the NMOS transistor T23 whose source is connected to the low-potential power supply VSS. The PMOS transistor T24 has a relatively large ON resistance and its gate is connected to the low-potential power supply VSS. Therefore, the PMOS transistor T24 is normally ON and serves as a resistor element.
The delay circuit 214 is comprised of an inverter circuit which has an input terminal to which the external input signal VIN is applied and an output terminal connected to the gates of the NMOS transistor T13 and PMOS transistor T21.
The output buffer circuit 211 operates as follows.
(1) When the external input signal VIN changes its level from the L level (the level of the low-potential power supply VSS) to the H level (the level of the high-potential power supply VDD), the PMOS transistor T22 is turned off immediately, and the NMOS transistor T23 is turned on, causing the control signal VN to rapidly fall to the L level from the H level. Therefore, the output transistor T2 is turned off immediately.
In response to the H-level external input signal VIN, the first (PMOS) transistor T11 is turned off immediately, and the NMOS transistor T12 is turned on. However, the H-level external input signal VIN which has been delayed by the delay circuit 214 is applied to the gate of the NMOS transistor T13. That is, the H-level inverted external input signal VIN before the change of the external input signal VIN is applied to the gate of the NMOS transistor T13 for a predetermined time. Therefore, the NMOS transistor T13 is enabled for a predetermined delay time so that the control signal VP rapidly falls as indicated by *1 in FIG. 3. When the level of the delay signal from the delay circuit 214 changes to the L level from the H level after the predetermined delay time passes, the NMOS transistor T13 is turned off so that the control signal VP gently falls due to the large ON resistance of the NMOS transistor T14. Therefore, the time needed for the first output transistor T1 to be turned on completely is longer than the time for the second output transistor T2 to be turned off, thus generating the external output signal VOUT that gently changes to the H level from the L level.
(2) When the external input signal VIN changes its level from the H level to the L level, the NMOS transistor T12 is turned off immediately, and the PMOS transistor T11 is turned on, causing the control signal VP to rapidly rise to the H level from the L level. Therefore, the first output transistor T1 is turned off immediately.
In response to the L-level external input signal VIN, the NMOS transistor T23 is turned off immediately, and the PMOS transistor T22 is turned on. However, the L-level external input signal VIN which has been delayed by the delay circuit 214 is applied to the gate of the PMOS transistor T21. That is, the L-level inverted external input signal VIN before the change of the external input signal VIN is applied to the gate of the PMOS transistor T21 for a predetermined time. Therefore, the PMOS transistor T21 is enabled for a predetermined delay time so that the control signal VP rapidly rises as indicated by *2 in FIG. 3. When the level of the delay signal from the delay circuit 214 changes to the H level from the L level after the predetermined delay time passes, the PMOS transistor T21 is turned off so that the control signal VN gently rises due to the large ON resistance of the PMOS transistor T24. Thus, the time needed for the second output transistor T2 to be turned on completely becomes longer than the time for the first output transistor T1 to be turned off, thus generating the external output signal VOUT that gently changes to the L level from the H level.
FIG. 3 shows the waveforms of the control signals VP and VN, the external output signal VOUT and a switching current I which flows through the output transistors T1 and T2. When the external output signal VOUT changes its level to the H level from the L level, as shown in FIG. 3, the control signal VP gently falls and the control signal VN drastically falls. As a result, the output transistors T1 and T2 are not turned on at the same time. At the time the level of the external output signal VOUT changes to the L level from the H level, likewise, the output transistors T1 and T2 are not turned on simultaneously. This reduces the current I that flows through the output transistors T1 and T2 at the time of switching, thus decreasing the consumed current of the output buffer circuit 211.
As the NMOS transistor T13 and the PMOS transistor T21 are turned on for the delay time of the delay circuit 214 at the time of switching, the control signals VP and VN drastically change as indicated by *1 and *2. Because the delay time of the delay circuit 214 is set to the time for the control signals VP and VN to reach the threshold voltages of the output transistors T1 and T2, the rising and falling responses of the external output signal VOUT become faster, thus decreasing the propagation delay time of the output buffer circuit 211. Since the slew rate of the external output signal VOUT is lower than that of the output signal of an ordinary CMOS inverter, the output buffer circuit 211 is suited for slow (low-frequency) data transfer.
In the case where the output buffer circuit 211 should be used for high-frequency data transfer, however, the control signals VP and VN cannot change in response to a high frequency, so that the external output signal VOUT cannot fully swing. When the external input signal VIN as shown in FIG. 4(a) is supplied to the output buffer circuit 211, for example, the control signals VP and VN cannot reach the H level and L level because of a fast change in external input signal VIN as shown in FIG. 4(b). As a result, the external output signal VOUT does not reach the H level (the level of the high-potential power supply VDD) as shown in FIG. 4(c). That is, the external output signal VOUT that has an H-level pulse width W2 narrower than an H-level pulse width W1 of the external input signal VIN is generated, which may cause an error in data transfer. The pulse width W2 also becomes narrower by variations in the process, temperature and supply voltage (PTV variations), which may result in malfunction.
To use the output buffer circuit 211 at a slower speed than the present operational speed, on the other hand, it is necessary to keep the voltages of the control signals VP and VN at an intermediate potential near the threshold voltages of the output transistors T1 and T2 for a long time. This however also raises the aforementioned problems that concern the full swing of the external output signal VOUT and the pulse width in the previous case.